Research on an active matrix light emitting device having a self-luminous element has been becoming more active. A typical example of such a self-luminous device is an EL display device.
In recent years, a flat panel display device which is widely used for a display portion of a portable information terminal as well as for a medium-size or a large-size display device has the increasing number of pixels in accordance with the high resolution. In accordance with the increase in the number of pixels, these displays employ pixels in an active matrix structure which has a thin film transistor (TFT) in each pixel and can store image data.
There are an analog gray scale method and a digital gray scale method in a gray scale method of an active matrix EL display device. The digital gray scale method has a time gray scale method, an area gray scale method, a method in which the time gray scale method and the area gray scale method are mixed, and the like. In either of the time gray scale method and the area gray scale method of the digital gray scale method, each pixel or subpixel is driven by binary values, namely an on state and an off state.
Accordingly, there is an advantage in that deterioration of image quality due to variations in a threshold voltage Vth of thin film transistors (TFTs) arranged in the pixel can be reduced as compared to the analog gray scale method. Patent Document 1 discloses a digital gray scale display performed by the time gray scale method.
Further, it is preferable for rapidly writing video signals to each of a plurality of pixels to employ a line sequential method in which data is inputted simultaneously per one row. Description is made with reference to FIG. 9 on an active matrix EL display device driven by the line sequential method to perform the digital gray scale display.
FIG. 9 shows a configuration of a display device driven by the digital gray scale method in which binary data is inputted to pixels in the active matrix structure. A pixel portion 501 includes a light emitting element typified by an EL element and a TFT for controlling light emission of the light emitting element. A source signal line driver circuit 502 including a shift register 504, a first latch circuit 505, a second latch circuit 506, a level shifter 507, and a buffer group circuit 508, and a gate signal line driver circuit 503 including a shift register 509, a level shifter 510, and a buffer group circuit 511 are arranged in the periphery of the pixel portion 501. FIGS. 10A and 10B show equivalent circuits of the buffer group circuit 508.
As shown in FIG. 10A, the buffer group circuit 508 includes a plurality of buffers 601 provided in each column. FIG. 10B shows an equivalent circuit of the buffer 601 which is formed of two inverters. An input of the buffer 601 is connected to the level shifter 507 and an output thereof is connected to the pixel portion 501. Further, a buffer high power potential (VBH) is applied from a signal line 602 and a low power potential (VBL) is applied from a signal line 603.
Description is made on a method for driving the active matrix display device shown in FIG. 9 by the line sequential method to perform a digital gray scale display. First, the shift register 509 outputs a selection pulse sequentially from a first stage in accordance with a clock signal (GCK) and a start pulse (GSP). After that, amplitude conversion is carried out by the level shifter 510, thereby gate lines are sequentially selected from the first row by the buffer group circuit 511.
In the selected row, the shift register 504 sequentially outputs sampling pulses from a first stage in accordance with a clock signal (SCK) and a start pulse. The first latch circuit 505 captures video signals (Video) at timing that sampling pulses are inputted. The video signals captured in each stage are held in the first latch circuit 505.
When a latch pulse (LAT) is inputted after video signals of one row are all captured, the video signals held in the first latch circuit 505 are transferred to the second latch circuit 506 all at once, thereby all source signals are charged and discharged.
At this time, the buffer high power potential (VBH) which charges and discharges the source signal line is in synchronization with a light emitting element high power potential (ANODE) while the low power potential (VBL) is fixed. In this specification, the light emitting element high power potential (ANODE) corresponds to a potential applied to an anode of the light emitting element.
The aforementioned operations are repeated from the first to the last rows, and thus data is written to all the pixels. Accordingly, an image corresponding to one frame is displayed. Similar operations are repeated to display images.
[Patent Document 1]
Japanese Patent Application Laid-Open no. 2001-5426